This nascent blog has moved to a new and more permanent home, at

http://www.fivecomputers.com

Each year, John Cooley does a great job previewing the companies at DAC. From that list, here’s the ones that sound interesting to me.

OneSpin’s 360MV tool does something called “gap-detection” plus timing diagrams on your design’s System Verilog Assertions. (booth 625)

Real Intent Meridian CDC for clock domain crossing verification. Formal analysis and interfaces to simulation.
(booth 2540)

NuSym DeNibulator’s intelligent testbench” It hunts down your hard to find coverage points and automatically tweaks your TB to reach them. It’s next gen constrained random. (booth 379)

Certess Certitude testbench error injection.(booth 324)

Another “intelligent testbench” is Mentor inFact – graphical tool that generates, grades, and then upgrades TBs. It
now drives existing e, Vera, SV, or C/C++ TBs. Does OVM & VMM.(booth 2301)

CebaTech is showing their C2R Compiler,which takes untimed ANSI C and outputs Verilog RTL. (booth 760)

Forte Cynthesizer v3.4 (SystemC design) adds support for Power Compiler for “best-in-class area, performance, and now power results” and “management of ECOs by graphically mapping RTL back to the original SystemC design” and inter-block interfaces.(booth 1645)

Mentor ’s Catapult C synth & Vista ESL tools. (booth 2301)

Carbon’s Model Studio does Verilog-RTL-to-C conversion for simulation, to get early models for architectural work(booth 2467)

Synfora Pico Extreme C synthesis tool (booth 329)

Bluespec : “general purpose high-level synthesis & simulationfor modeling, verification and implementation”. (booth 2367)

Imperas : yet-another-ISS tool, OVPsim, for embedded SW. (booth 467)

Mirabilis VisualSim does “graphical SystemC TLM 2.0 import without any code development; and power estimation of the full system.” (booth 778)

Steve Golson’s “Four Principles of Flow Engineering” DAC Tuesday at 10:30 AM, Room 206AB

Dassault Synchronicity DesignSync Cadence data management tools. (booth 620)

EVE ZeBu is showcasing PCIe and AXI synthesizable transactors and its System Verilog support for custom transactors.(booth 301)

Mentor Veloce “using mixed System Verilog and SystemC based upon System Verilog DPI standard 2.0″ with Nucleus embedded RTOS (booth 2301)

Synfora Pico Extreme FPGA (booth 329)

VeriEZ EZVerify covers you design, assertions and testbench, with added full System Verilog support this year plus VMM/OVM checking (booth 1936)

Veritools usually has linters, code coverage and waveform viewers. Supports SV dynamic objects. (booth 1334)

Denali PureSpec System Verilog methodology support (OVM,VMM, AVM) in all IP blocks. (booth 1611)

A great example of the sort of insight that you can glean from a lot of data, with the right sort of visualisation. Also a painful example of the limitations of a wordpress blog. I can’t embed TED talks here, so I’ll just link to it. Frustrating.

Based on the list of exhibitors and the scant information provided, these are some of new companies that appear to have a verification aspect to their products. I’ll be finding out more next week on site. Brian Bailey has his take on DAC for Verification, over at Chip Design mag, that is worth a look if you are struggling to fill your schedule! There is quite an overwhelming amount of things packed in to next week.

• Amiq Consulting S.R.L.1

RTL level verification & verification IP

• Axilica Ltd.

Tools for UML modeling/simulation of HW/SW designs

• Duolog Technologies Ltd.

Intelligent testbench, ESL verification – Socrates design environment

• Imera Systems, Inc.

Network virtualisation, remote debugging and source code access

• Paradigm Works, Inc.

Verification services company. Selling SystemVerilog FrameWorks tools

• SAS Satin IP Technologies

Design reuse management flows & technology. VIP lane product for IP deployment

• Synapse Design Automation

Design & Verification services company

• WinterLogic Inc.

Verilog fault simulator company: Fault Manager

I haven’t been to the Design Automation Conference (DAC) for several years. Last time I was there, SystemC was the hot new language on the block, ready to revolutionise the design and verification world. In the intervening years, the hype has died down a bit and SystemC has settled into a comfortable niche as a solid option for doing higher level modeling, that previously was done in a roll your own C or C++ environment. The features for modeling parallelism and communication along with structure are good enough to mean you don’t need to do it all from scratch. The speed is slowly getting better, but it isn’t going to change the design world. It somewhat dropped the ball by being implemented as a set of library extensions to C++, rather than an enclosed language (which would have had the potential at least to be synthesisable – something SpecC got right).

Now several years later, the hot new language on the block, ready to revolutionise the design and verification world is SystemVerilog. Low level enough to write hardware. Feature rich enough to support verification. An IEEE standard (that nobody quite implements). All things to all people. Maybe. Or maybe 3 distinct languages that happen to run together on one simulator – which seems closer to the reality. A step in the right direction perhaps, and certainly the current flavour of the month. OVM and VMM (verification libraries built on top of SystemVerilog) are the thing that kept coming up time and again as I looked through the DAC sessions, with an eye towards verification and system-level design. With the news that the VMM is open source, along with the already freely available OVM, perhaps the opportunity to merge to one set of libraries across the big three has some potential, if we ignore all the legacy investment that will still need to be supported.

These are the sessions that caught my eye at this year’s DAC and that I hope to attend. I’m surprised quite how many of them overlap, so I suspect I’ll be missing more than I might like. There is so much going on this year! I plan on blogging throughout the conference and sharing the interesting things I find.

Monday 9th June

Find the Toughest Bugs with Mentor Graphics 0-In Formal Verification
Migrating to OVM for Multi-Language Verification
Gary Smith on EDA: Trends and What’s Hot at DAC
Real World Advantages of the OSCI TLM-2.0 Standard for Model Interoperability and IP Reuse

Tuesday 10th June

Catapult & Vista: Integrating ESL Synthesis & Verification
Experiences and Advances in Formal and Dynamic Verification
Formal Verification Technology
Innovation in Verification Luncheon
Multi-processor SoCs: The Next Generation
iDesign II – practical aspects of using SystemVerilog

Wednesday 11th June

Getting Real With OVM, A True Open Source Verification Standard
Challenges on Design Complexities for Advanced Wireless Silicon Systems
Verifying Really Complex Systems: On Earth and Beyond
Wild and Crazy Ideas

Thursday 12th June

Advances in Verification of Abstract (pre-RTL) Models
Closing the Loop in Intelligent Testbench Automation
Your Functional Verification Roadmap: OVM, VMM, or Roll Your Own?
Formal Verification: Dude or Dud? Experiences from the Trenches

Thomas J. Watson, the president of IBM, once famously didn’t say that I think there is a world market for maybe five computers. He is still widely quoted as having said it and it is usually trotted out as a good example of why we shouldn’t make predictions about the future of technology. Mainly because those predictions almost always will make us look entirely foolish. The title of this blog is based on that quote, in the hope that it’ll discourage me from making too many painful statements about what I think the future of EDA and verification might be, but that’s what this blog is going to be about.

Electronic design automation and functional verification are two pieces of the puzzle aiming to help close the design gap in the semiconductor industry. That’s the gap between the amount of transistors we can put on a piece of silicon and the amount of transistors we can usefully put together to produce a working system that does something useful, in a reasonable period of time. The device physics guys have done a great job of getting well ahead of what we can usefully design. The main gap doesn’t really seem to be what can be designed, though. It is what can be tested and verified to actually do what it is supposed to do.

There are more challenges further down the pipe too, timing closure looms ever larger as a problem, further reduction in geometries threaten the basic assumptions that let us typically ignore the nasty analog reality and pretend we are in some digital fantasy of ones and zeros. Those are all big problems or at least getting bigger, but functional verification is swallowing vast amounts of engineering time on projects right now and we seem to be getting ever further behind the curve. ( I feel already that I’ve made two potential 5 computers kind of statements in just this one paragraph.) EDA tools keep promising great leaps forward, but we still seem to be seeing the same promises and not so much progress. Raising the abstraction level of the design languages, increasing the quality of the verification, more reuse and large amounts of money invested in creating IP, but largely the industry still appears to be where it was 10 years ago – just with more people working ever harder on each product.

The one saving grace in all this is that there is quite the demand for semiconductor devices. If you start counting up all the computers, portable devices, smart cars and embedded processors in use around your life, you’ll probably quite quickly realise you’ve maxed out that world market for 5 computers all on your own. In fact it is probably closer to 50 computers or computing devices in use around you. So at least the demand for products is there, even if we aren’t quite sure how to design them all effectively, yet.